Testing Components: That’s All You Have To Do In Testing
Briefly speaking, they consist of internal tests, which are normally DFT oriented, functional tests, parametric tests and environment tests. This section is going to talk about what they are and how they impact your testing life.
ATE & IC Testing: Too Expensive to Ignore It
What cause ATEs expensive are the precision, speed, memory, channels and integration of digital and analog test functionalities. What do the ATE specs mean to you? Topics include waveforms, strobes, PMU, cost estimation, breakeven point calculation, etc. How they associate with IC testing. Availability and specifications of ATEs limit your design flow, test strategy and time-to-market.
Trend in ATE: structural tester, low cost tester. What they do and how they reduce your cost.
Traditional Testing: More Challenges And Expensive
Event driven and cycle based tests. How people develop the functional patterns for digital IC: verilog testbench to VCD. Advantages and disadvantages of functional tests. ATEs and functional tests. What are parametric tests? Open/short tests. IDD Test. Output voltage testing. Input leakage testing, Tristate leakage test. Wafer sorting. Testing Pies (overlap of different type of patterns detecting faults).
Test Economics: My Managers’ Jobs
Moore’s cycle. Test preparation (DFT logics, test-related silicon., pattern generation, pattern simulation, and tester program generation). Test execution (DUT card design, probe cards, temperature generator, handler, drier, production test time, IC debugging, ATE cost). Test escape cost. Defect level (Yield loss vs Test coverage). Diagnosis, Failure analysis. Cost of failure at different stages. Time-to-market, time-to-yield.
Test cycle (test time) calculation.
Test economics drives DFT technology, low cost DFT oriented tester and standard test program.
--Scan and Faults: Cornerstone Of DFT technology
Common scan types. Scan variations. How scan work? Scan in ATPG. Scan in BIST. Scan in Boundary scan. DC scan, AC scan (LOS, LOC). How defects are modeled? Fault types.
--Test Synthesis: Key To High Test Coverage And Design Penalty
Scan insertion. Partial scan, full scan. Scan assembly, chain balance, lockup latch placement. Dealing with the multiple phase clocks. Bottom up and top down test synthesis. How to deal with multiple types of scan cells. Test Synthesis rules.
-- DRC rules: The Bridges To Success
Clock rules, bus (bidi) rules, AVI rules, data traction rules, memory test rules, scan tracing rules.
--ATPG and Pattern generation: Let Machine Do It??
ATPG algorithm. Procedures. True beauty of fault simulation. How to fault simulation functional patterns in ATPG? Bus contention in pattern generation. Abort limit. Sequential ATPG.
Pre-shift, post-shift, end-measurement. Strobe edges: where do I put them (give out an example)
Fault collapsing. Why ATPG untestable, why DI, UU, TI, BL, RE etc. What’s the atpg? effectiveness? What’s the test coverage and fault coverage? How do you calculate the test coverage? How to increase the test coverage? On chip PLL testing (new method in ac scan). Z masking, padding. Scan cell mask, outputs mask in transition faults.
--BIST: Pros And Cons
Memory faults. Memory testing methods. Embedded memory testing, at-speed memory testing. Logic BIST structural, the benefits and the penalty. LBIST flow: phase shift, PRPG, MISR, x-bounding. At-speed logic BIST. ATPG top-up in logic BIST design.
--Boundary Scan: Don’t Think It’s Too Simple
Structure of Boundary scan. Can control Memory BIST, LBIST, ATPG (state machine analysis plus an example). Can do board testing (JTAG technology, Asset International). An example on atpg through boundary scan.
--Pattern Optimization and Technology: Great Area to Hammer DFT
Pattern compression during ATPG. Pattern ordering. EDT technology, DBIST, XDBIST (deterministic BIST). Macro pattern, fault simulation. Transition pattern generation to iddq pattern generation.
--Diagnosis: Did I Really Do Something Wrong?
Scan logs. How many failed patterns you need to do diagnosis? What does the values mean in fault simulation and good simulation values. Memory BIST diagnosis. LBIST diagnosis: the difficult thing. How to correlate the pattern with signature?
--IDDQ pattern generation and Analysis: This Is Analog!?
IDDQ analysis. How leakage current estimated. Pull up, pull down in IDDQ pattern generation. Tristate in iddq pattern generation. How to efficiently generate IDDQ pattern. Delta IDDQ. Delta IDDQ in wafer sorting.
--DFT flows: Yes, That’s Where I Am Now
a) SOC test: directly test big memory through MBIST, macro test embedded small memory, black box analog module, ATPG, pattern simulation, mismatch debugging, diagnosis.
c) Multiple identical module testing: pin sharing; xor scanouts (aliasing)
d) Fault simulating functional pattern, ATPG.
e) LSSD design flow.
f) MBIST flow
g) LBIST flow
IEEE Testing Standards and EDA Tools: Do They Matter to Me?
Why each tester has its own hardware language?
IEEE 1450.1 STIL: the new trend in test language. Structure, waveform definition. (an atpg with boundary scan example)
IEEE 1450.6 CTL
Engineering IC Debugging: DFT Engineers Hate It
DC conductivity. Chain tests: diagonal chain pattern. Edge adjustments. Timing factor. DC, scan debugging. AC scan debugging. IDDQ debugging. Shmooing, strobe, clock edge, power supply setup. Two dimension shmooing. Three dimension shmooing. Clock dependency. Flaky results (an example scan chain debugging). Power on order. Probe clk, probe scan-enable. Setting up trigger. Calibration. Pattern qualification, verification.
PAN-PAC TECHNOLOGY is a consulting oriented Hi-Tech company based at Portland, Oregon, USA, the 3rd largest semiconductor center in USA. Its focused area is for IC testing consulting, ATE analysis, Formal Verification consulting, analog design consulting etc.